Low-cost FPGA family offers multiprotocol 3.2-G SerDes

65-nm devices are said to offer lowest power consumption available
The third-generation low-cost 65-nm LatticeECP3 FPGA family offers multiprotocol 3.2-G SerDes with XAUI jitter compliance, DDR3 memory interfaces, and DSP capabilities. The devices have 17-K to 149-K logic elements and are said to take 85% less static power and 50% less dynamic power than equivalent Virtex and Stratix parts